FPGA Development Engineer

Our long-term corporate strategy aims equally at satisfied employees and customers. We would therefore be delighted to welcome you to our highly qualified team at HESYS in the future.

For a project assignment with our well-known international client from the high-tech industry in Taufkirchen near Munich we are looking for you as FPGA Development Engineer.

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RESPONSIBILITIES

You will work as a FPGA Development Engineer and will support the design center Telecom & Navigation Processing Germany which specializes in high performance processing solutions for satellites. The research and development focus are satellite on-board processing applications, e.g. for future telecommunication or navigation payloads.

Digitalisation of satellites is key to provide more services and more flexibility for telecommunication and navigation space industry. The digital processing products of the design center in Ottobrunn can be reprogrammed for a new mission within minutes from control centres on the ground. Emergency services will then be able to exchange information, coordinate their activities and rescue people in crisis areas with no means of communication.

In addition, edge applications are on the roadmap for future 5G/6G infrastructures where satellites are seen as possible "datacenters in space", where processing can be provided on-board. The current position will support the on-going development on the new generation of telecommunication or navigation on-board processor equipment.

These are the main tasks:

- Analysis of requirement specification and generation of architectural concept of processor and FPGA functions, Hardware Software partitioning for System-on-Chip components

- VHDL Detailed Design for Xilinx and Microsemi FPGAs and analysis of the designed components in regard to the appropriate VHDL guidelines and with use of the respective tools and checklists

- Develop software for system-on-Chip processors (optional)

- Develop and simulate algorithms as part of the SoC designs using Matlab and transfer function from Matlab model into VHDL

- Simulation of the designed VHDL components using Mentor Questa Tool environment

- Synthesis, Place and route to generate the FPGA programming file

- Generation of the technical documentation

- Support of hardware commissioning tests of the FPGA

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QUALIFICATIONS

- Degree in engineering or industrial engineering or Computer Science or comparable

- Experience with VHDL Design and Verification for FPGAs is necessary

- Experience in partitioning of HW/SW functions into FPGA or MPSoC Architecture is required

- Proven experience with algorithm developments using Matlab is required

- Good knowledge of Software Programming of Embedded Systems is required

- Experience with analysis tools to check coding rules and code coverage is necessary

- Experience with Mentor Questa Tool Environment is necessary

- Language skills: English business fluent, German would be a plus

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HESYS TechnicalSystems GmbH & Co. KG

Tel: +49-89-6131287

E-Mail: careers@hesys-engineering.de

Internet: www.hesys-engineering.de